U.S. Pat. No. 4,012,757 to J. T. Koo discloses an MOS random access memory in which data is stored in the form of charges in capacitive memory locations. In such a structure, leakage currents cause the stored charges to decay with time. Consequently, to retain stored data in the memory locations over an extended period of time, periodic readout and refresh pulses become necessary.
Memories subject to these periodic readout and refresh pulses are referred to as dynamic random access memories or dynamic RAMs. While the dynamic RAM device structure is simpler than a static RAM device structure and therefore more desirable, in making such a dynamic RAM it is also desirable to minimize the decay of the stored charges.
A longer decay time amounts to the possibility of slowing down the frequency of the refresh pulses. A longer decay time also decreases the possibility of losing stored data during the interval between two consecutive refresh pulses. Since there is a relationship between the rate of decay of the stored data and the reverse biased junction-type leakage current in the device, it, of course, becomes desirable to reduce this leakage current.
U.S. Pat. No. 3,997,368 to Petroff et al. entitled "Elimination of Stacking Faults in Silicon Devices: A Gettering Process" discloses a reduction of p-n junction leakage currents by suppressing the formation of crystal defects near p-n junctions in semiconductive material through a gettering process. The gettering includes the introduction of lattice distortion by forming a stressed layer on the back surface of the wafer. The layer is then annealed for a time and a temperature effective to cause stacking fault nucleation sites to diffuse to a region near to the back surface of the wafer. The diffusion of the nucleation sites to the vicinity of the back surface suppresses the formation of stacking faults in the device.
Gettering processes similar to those described in U.S. Pat. No. 3,997,368 have been used in the manufacture of typical dynamic memories. For such memories typical hold times have been found to lie in the order of 6 to 40 milliseconds at an 85.degree. C. junction temperature. The term "hold time" refers to the time interval at which refresh pulses can be spaced without losing information from the memory cells.
Of course, for any number of memories tested, hold times vary within a range. By the term "typical" with respect to hold time values it is intended to specify values which divide any number of devices into two substantially equal groups of devices, one group with longer, the other with shorter hold times. It, therefore, appears desirable to manufacture dynamic memories with typical hold times well above minimum hold time requirement. To obtain an acceptable yield of manufactured memory devices, it is desirable to have substantially all such devices meet the minimum hold time requirements.
It has been recognized, for instance, by the aforementioned U.S. Pat. No. 4,012,757 to J. T. Koo that MOS random access memories can be made in a semiconductive body which comprises a substrate portion on which there has been grown an epitaxial layer in which the active cells of the memory are formed. However, there are no such known memories which have become commercial. This is believed to be the case because hitherto any reasonably expected benefits of such a structure could not outweigh added process complexity and expense of the addition of an epitaxial layer to bulk silicon.